Industries · Telecom & data-centre hardware
Assembly for switch and router line cards, optical modules, base-station processing boards and backplanes, where 25 / 56 / 112 Gbps PAM4 signalling, back-drilling and controlled impedance set the bar. Press-fit holes are drilled to 0.46 mm ±0.025 mm, and that drilling tolerance is a bare-board parameter, not our machining tolerance. Bare boards sourced from audited partner fabs, with incoming inspection and full lot traceability; layer count, back-drilling and impedance coupons sit with the fab, while we own assembly and documentation. Our assembly envelope is 0.4–4.0 mm board thickness, and a 5.2 mm large-format board is outside it — you will hear that at DFM stage, not after tooling. Assembly lead time ex-components.
Why the tolerance is this tight
Nobody specifies a residual stub budget or a press-fit hole tolerance for its own sake. They specify it because the cost of an outage and the cost of a re-spin are both measured in six figures, and because the racks these boards go into are outgrowing the halls built for them.
High-layer-count boards run 20–68 layers, with production backplanes at 20–36 layers. Every unused via barrel is a stub that reflects energy at these rates, so back-drilling depth and residual stub targets are set by the stack-up long before assembly. A documented 48-layer 400G board measures 350 × 450 mm, 5.2 mm thick, with a 17:1 aspect ratio and 85 Ω differential impedance.
More than 90% of mid-size and large enterprises report downtime costs above USD 300,000 per hour, and 41% report USD 1M–5M per hour. The figure is a benchmark, not a target — but it explains why this vertical audits process records and materials documentation as closely as it audits the board.
An average PCB design re-spin costs about USD 28,000 and adds four to eight weeks. When a stack-up error or a missed impedance target causes that turn, the schedule damage usually exceeds the cost — which is why impedance coupons and stack-up documentation are requested from the fab before assembly is quoted.
A GB200 NVL72 rack draws about 120 kW nominal and 130–132 kW under full load, against a conventional air-cooling ceiling near 20–30 kW per rack. That gap moves heat management onto the board and into the assembly: copper weight, thermal interface materials, press-fit current paths and rework access all become first-order constraints.
Large-format multilayer boards warp, and warpage shows up as placement offset and as press-fit connectors that will not seat cleanly across a full connector bank. Panel support, reflow support tooling and connector seating force have to be planned for the board, not inherited from the previous product.
Dense BGA fields hide their joints, so void acceptance and X-ray coverage have to be agreed before the build rather than argued about afterwards. Rework access on a fully populated 400 mm board is limited, and a joint that cannot be reworked reliably is a scrap decision rather than a repair one.
Responsibility boundary
This is the table that matters most on this page. Parameters in the bare-board column are not our manufacturing capability, and claiming them would fail your audit at the first question. Where a parameter spans both scopes, both are stated.
| Parameter | Values | Owner |
|---|---|---|
| Layer countHigh-layer-count construction | Production backplanes run 20–36 layers; high-layer-count fabrication spans 20–68 layers. A documented 48-layer 400G switch board measures 350 × 450 mm, 5.2 mm thick, with 0.30 mm minimum mechanical drill, a 17:1 aspect ratio and 85 Ω differential impedance. | Bare-board fab — we assemble on the finished board |
| Back-drilling and residual stub | Back-drill depth control and residual stub length are fab processes, typically held to a depth tolerance around ±0.1 mm with a residual stub of 0.2–0.3 mm. | Bare-board fab — verified on incoming documentation, not produced here |
| Impedance and stack-up | Single-ended and differential targets are typically ±10%, and the stack-up and target impedance must be supplied with the fabrication package. Impedance test coupons are produced and measured by the fab. | Bare-board fab — we assemble to the released stack-up and check incoming documentation |
| Press-fit holes | Holes are drilled to 0.46 mm ±0.025 mm, a drilling tolerance owned by the fab. Backplane construction also specifies plated barrel copper thickness separately from that hole tolerance. | Drilling is fab-side; press-fit insertion is assembly-side and is ours |
| Board thickness and format | Large-format boards in this segment reach 5.2 mm. Our assembly envelope is 0.4–4.0 mm, so a board at that thickness is outside what we can build — and we say so at DFM stage rather than after tooling. | Assembly-side envelope — stated up front, not discovered later |
| Acceptance and traceability | IPC-A-610 Class 2 is the default for telecom hardware and Class 3 can be specified. Traceability is lot-level, ESD control follows ANSI/ESD S20.20 practice, and RoHS and REACH declarations are issued as documents. | Assembly-side — we own the solder acceptance criteria and the records |
Capability match
We publish no anonymised telecom case here — our case set does not cover this vertical, and we will not invent one. Every other industry page on this site carries a real anonymised record; this page carries a capability statement instead, because a fabricated case would be worth less than the gap it fills.
Press-fit connector insertion is the defining assembly operation in this segment. Connectors are seated with controlled force into the drilled holes, and the process is planned around the connector bank rather than applied per pin, because a partially seated press-fit connector is a field failure that no board-level test reliably catches.
Mixed-technology and selective soldering cover the through-hole content around the press-fit field — power connectors, mounting hardware and shield cans — with robotic single-nozzle selective soldering keeping thermal load away from adjacent surface-mount devices. Board thickness spans 0.4–4.0 mm.
Inspection scope is configured per project: 3D SPI on print, AOI after reflow, and X-ray where BGA or hidden-joint coverage is called for. We do not run X-ray on every board as a blanket rule, and we will not describe inspection as 100% of anything.
Documentation is where an assembly partner earns its place in a NEBS submission. We supply process records, materials and compliance declarations, lot-level traceability and inspection data for the buyer's own submission to the carrier — we do not claim to have passed NEBS, because NEBS applies to the equipment, not to a contract assembler's process.
Straight answers
High-layer-count boards within an assembly envelope of 0.4–4.0 mm board thickness, with press-fit connector banks, mixed through-hole and surface-mount content, and large-format panels that fit our line. Boards above the thickness envelope, or panels beyond our handling format, are identified at DFM stage before tooling is cut.
Envelope: 0.4–4.0 mm · press-fit seating supported
Lot-level traceability covering the bare-board lot, component lots and process records; SPI, AOI and project-configured X-ray data; first-article inspection reports with the acceptance criteria applied; RoHS and REACH declarations on request. These are the process and materials records your NEBS submission asks a supplier for.
Output: lot records · inspection data · declarations
Layer count, back-drilling, impedance coupons and press-fit hole drilling belong to the bare-board fab, and we do not present them as our capability. Boards outside our 0.4–4.0 mm assembly envelope are declined at DFM stage, and if the segment's 5.2 mm large-format construction is what your design needs, you will hear it in the first review rather than after stencils are made.
Boundary: fab parameters and out-of-envelope formats
Next step
We will tell you within the first review whether the board sits inside our assembly envelope, which parameters belong to your fab, and what documentation we can supply for your carrier submission. If the design is outside what we can build, you will hear that before any tooling is cut. Assembly lead time ex-components; long-lead semiconductors can add 12–26 weeks.
Reply within one business day
Telecom boards are dominated by large packages and connectors, so most programmes start at 100 pcs plus 50 spares. Small chip passives alone can begin at 50 pcs plus 30 spares.
Related reading: all six industry pages, quality and inspection scope, and assembly capabilities.