Solder paste printing
Gate: paste volume and aperture fill, printed through the laser-cut nano-coated stencil.
SMT ASSEMBLY · 01005 TO 100 × 90 MM
SMT assembly from 01005 to 100 × 90 mm.
Placement accuracy is ±25 µm across 7 SMT lines, with QFP leads and BGA balls down to 0.4 mm pitch, held by a 3D SPI closed loop on volume, height, area and offset. Boards whose smallest package or finest pitch falls outside that window are sent back to you at DFM stage, before a stencil is cut.
CAN YOU PLACE IT AT ALL
Four numbers decide whether your board runs here
These are the four values a process engineer checks first. Two are line capability, one is a machine rating, one is a machine rating you should not read as output.
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01005 / 03015
smallest chip placed
Imperial 01005 and metric 03015 chip components, printed through a laser-cut stainless stencil with a nano coating.
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0.4 mm
QFP lead and BGA ball pitch
QFP lead pitch and BGA ball pitch both reach 0.4 mm, which is the point where stencil nano coating stops being optional.
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±25 µm
placement accuracy
Machine rating for the Panasonic NPM-D3 placers that make up the 7 SMT lines.
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84,000 CPH
rated placement speed
Rated components per hour per machine, quoted from the equipment specification. It is a rating, not achieved output.
FULL PROCESS WINDOW
The complete window, parameter by parameter
Fifteen rows, in the order a DFM review checks them. The basis column says where each value comes from, so you can tell a machine rating from a standard clause.
| Parameter | Value | Basis |
|---|---|---|
| Minimum chip component | 01005 (imperial) / 03015 (metric) | Line capability, both package systems run |
| Maximum component | 100 × 90 mm, up to 28 mm tall | Line capability |
| Stacked packages | PoP (package-on-package) | Line capability |
| Minimum QFP lead pitch | 0.4 mm | Line capability |
| Minimum BGA ball pitch | 0.4 mm | Line capability |
| Placement accuracy | ±25 µm | Panasonic NPM-D3 machine rating |
| Rated placement speed | 84,000 CPH per machine, 7 lines | Machine rating, not achieved output |
| Sustained output | ≈5,600,000 placements/day | Derived: 7 lines × 84,000 CPH × 24 h × 40% overall equipment effectiveness |
| Board thickness | 0.4 – 4.0 mm | Line capability |
| Stencil construction | Laser-cut stainless steel, nano coating | Print process standard; area ratio ≥0.66, aspect ratio ≥1.5 |
| Solder paste | Lead-free SAC305 | Automatic printer with 3D SPI closed loop |
| Reflow oven | 10-zone forced-air, peak 240–250 °C | Absolute ceiling 260 °C per IPC/JEDEC J-STD-020 |
| Reflow atmosphere | Air, or nitrogen at O&sub2; ≤1000 ppm | Project option, specified on the traveller |
| Panelisation | Array, V-CUT or stamp holes; process edge ≥5 mm | Design rule; V-CUT needs board thickness ≥0.8 mm |
| Depanelisation | Router or V-CUT | Line capability |
Acceptance to IPC-A-610 Class 2 / Class 3, workmanship to IPC J-STD-001, stencil design to IPC-7525B, reflow ceiling to IPC/JEDEC J-STD-020, BGA voiding to IPC-7095.
WHERE THE DEFECTS COME FROM
60–70% of SMT defects start at the stencil
Industry data puts 60–70% of surface-mount assembly defects in the printing step, so that is where the closed loop is installed. The 3D SPI sits directly after the printer and writes corrections back to it, rather than reporting a paste problem after reflow has already buried it under a component.
StencilLaser-cut stainless steel
Surface treatmentElectropolished, nano coated
Area ratio (IPC-7525B)≥0.66
Aspect ratio (IPC-7525B)≥1.5
Aperture wall taper1–3°, widened to 5–10° on request
0.4 mm BGA aperture1:1 with pad, never below 90%
QFN / BGA thermal padWindow-pane 4 / 6 / 9, 60–75% coverage
SPI closed loopVolume · height · area · offset
THERMAL WINDOW
What your board is actually exposed to
Alloy choice moves the whole profile. SAC305 is the production default; the low-temperature and high-temperature alternatives are quoted when the component list demands them.
Reflow zones10-zone forced-air convection
Production alloyLead-free SAC305, liquidus 217–220 °C
Peak temperature240–250 °C
Time above liquidus40–90 s
ΔT across the board at peak<10 °C
Absolute ceiling260 °C per IPC/JEDEC J-STD-020
AtmosphereAir, or nitrogen at O&sub2; ≤1000 ppm
LINE SEQUENCE
Six stations, six control gates
Every panel walks this order. Each station holds one decision it is allowed to stop the board on.
3D SPI
Gate: volume, height, area and offset against the acceptance window; out-of-limit boards are cleaned and reprinted.
Placement
Gate: package-to-footprint match and feeder verification before the first board of the run.
Reflow
Gate: profile within the 240–250 °C peak window and under the 260 °C ceiling.
AOI
Gate: 2D or 3D optical inspection for missing parts, offset, polarity, bridging and insufficient solder, configured per project.
Depanel & pack
Gate: router or V-CUT separation, edge inspection, then ESD bag and moisture-barrier packing.
PACKAGE FORMS
Six build types this line handles
MICRO CHIPS
Chip components from 01005
01005 (imperial) and 03015 (metric) parts need the nano-coated stencil plus a home-plate aperture reduction of 5–10% of pad area to stop tombstoning on the smallest passives.
FINE PITCH
Fine-pitch and array packages
QFP leads and BGA balls at 0.4 mm pitch, plus CSP, QFN and LGA. Paste targets at that pitch are 8,000–14,000 mil³ per pad with offset held under 50 µm.
STACKED
PoP and tall components
Package-on-package stacking and components up to 28 mm tall, including odd-form parts that need a dedicated nozzle and a verified placement force.
DOUBLE SIDED
Second-side reflow
Second-side reflow on carriers, down to 0.4 mm board thickness. The carrier and the reflow support plan are quoted with the build, not added afterwards.
PIN-IN-PASTE
Through-hole parts in the reflow pass
Pin-in-paste puts through-hole parts through the same reflow cycle as the SMD side, using 2–3× the normal paste volume from a stepped stencil or a print-plus-dispense step.
MULTI-UP
Panelisation and depanelisation
Array panelisation, V-CUT and stamp holes, with a process edge of at least 5 mm, stamp-hole pitch of 0.5–1.0 mm and V-CUT limited to board thickness of 0.8 mm and above.
MATERIALS AND CONSUMABLES
What you can specify
ALLOY
Solder paste and alloy
SAC305 lead-free is the production default. Alternatives are quoted per build: Sn42/Bi58 with a 138 °C liquidus and a 170–180 °C peak for temperature-sensitive assemblies, SAC105 at a 227 °C liquidus and 245–260 °C peak, or SN100C at a 227 °C liquidus and 250–260 °C peak. All alternative windows are industry-typical values.
STENCIL
Stencil and aperture treatment
Laser-cut stainless steel with electropolished walls to remove laser micro-ridges and a hydrophobic nano coating on top. Wall taper is naturally 1–3° and can be opened to 5–10°. Aperture strategy follows the package: 1:1 for BGA, window-pane 4/6/9 splits at 60–75% coverage for thermal pads.
ATMOSPHERE
Reflow atmosphere
Air, or nitrogen at O&sub2; ≤1000 ppm where the assembly is head-in-pillow sensitive or fine-pitched. Nitrogen drops the oxygen level from the 20.9% found in air to somewhere in the 100–1000 ppm band, which is the range head-in-pillow prevention targets.
CARRIERS
Carriers and panelisation consumables
Second-side reflow carriers and synthetic-stone pallets, quoted with the build. Panel design holds a process edge of at least 5 mm and a stamp-hole pitch of 0.5–1.0 mm; both are in the DFM checklist before release.
COMMERCIALS
Lead time, minimum order and engineering charges
Every date below is an assembly lead time ex-components: it starts when the last component is kitted, not when the order is placed. The bottleneck in this trade is normally the component, not the line.
Minimum order, chip passives 0603–2225, SOT, SOD, MELF50 pcs + 30 spares
Minimum order, all other packages100 pcs + 50 spares
Prototype quantitiesQuoted per order
1–10 pieces3–7 working days
10–1,000 pieces5–10 working days
5,000 piecesAbout 3 weeks
Volume, after components are kitted3–4 weeks ex-works
NREUSD 0–150, waived on most projects
StencilUSD 1.53–65 by size; framed from USD 80
Unit premium, 5–20 pieces+30–40%
Unit premium, 101–499 pieces+5–15%
Long-lead semiconductorsCan add 12–26 weeks
WHERE THIS LINE IS USED
Six sectors that buy this process
Industrial automation
Control and PLC boards
Wide-temperature components, 15-year availability planning and 2–3 engineering changes inside a PLC-grade lifetime.
Medical devicesMonitor and diagnostic boards
Lot-level traceability, IQ/OQ/PQ validation documents and change control on every process change.
Automotive & EVPower and control assemblies
IATF 16949 with the product-design exclusion, PPAP documentation and −40…+125 °C thermal cycling.
Consumer & IoTCompact wireless products
Week-scale iteration, cost step-downs and antenna and shielding layout settled before the radio module is certified.
Energy & powerConverter and meter boards
Heavy copper from 2 oz to 6 oz, high creepage distances and a 15–25 year field life to design for.
Telecom & data centreHigh-speed digital boards
Dense area-array packages, controlled impedance and X-Ray review of voiding under the largest devices.
Related lines: all capabilities · through-hole & DIP · testing & inspection · prototype to production · quality
NEXT STEP
Send the stackup and the smallest package
Tell us the thinnest board, the smallest chip and the finest pitch on the design. If any of the four numbers at the top of this page falls outside the window, we will say so at DFM stage instead of discovering it at first article.
Reply within one business day
Useful with the enquiry: board thickness, panel drawing, stencil aperture notes, target alloy and whether nitrogen reflow is required.