3D SPI
Paste volume, height, area and offset, with the result written back to the printer before placement begins.
TESTING & INSPECTION · SPI, AOI, X-RAY, ICT, FCT
Inspection data for the joints you cannot see.
Voiding under a ball-grid array is judged to IPC-7095 rather than to opinion, while 3D SPI watches paste volume, height, area and offset and 2D X-Ray looks through the packages that hide their joints. In-circuit test runs at 5–30 seconds a board; fixture NRE runs from USD 2,000 to USD 50,000+. Test items are configured per project and listed one by one on the quotation.
THE PROBLEM THIS PAGE SOLVES
Four joint families a camera cannot reach
A soldering defect under a package is invisible from above. The whole argument of this page is what we can show you about those joints, and what remains outside the reach of the equipment.
Hidden joint locationsBGA, CSP and QFN terminations
What 2D transmission seesVoiding, bridging and missing balls under area-array packages
Where it strugglesOverlapping layers inside a multilayer BGA
When 3D CT is the answerPer-layer slicing, 1–5 minutes per board section, definitive for void measurement and crack detection
THE ACCEPTANCE LINE, BEFORE ANY EQUIPMENT LIST
IPC-7095 void criteria
This is the block to copy into a supplier audit report. Both classes are judged on void area as a share of pad area, per joint and across the package.
Class 2 · individual void≤25% of pad area
Class 2 · total voiding≤40%
Class 3 · individual void≤10% of pad area
Class 3 · total voiding≤25%
Governing standardIPC-7095
Workmanship classIPC-A-610 Class 2 or Class 3, as named on your drawing
Class 3 position on X-RayMandatory under IPC-A-610, not optional
EVERY DETECTION PARAMETER
What is measured, and to what resolution
Nineteen rows covering paste, optical inspection, X-Ray, electrical test, environmental screening and documentation. Rows marked industry-typical are published process windows for this equipment class, not measurements taken on our own line.
| Parameter | Value | Basis |
|---|---|---|
| 3D SPI | Volume, height, area and offset, closed-loop back to the printer | Line capability |
| SPI acceptance window | Volume ±50% of nominal; height ±30% of stencil thickness; area ±50% of pad; offset ±25% of pad width; zero tolerance on bridges | Industry-typical values |
| SPI resolution, phase-shift profilometry | 10–15 µm lateral, 1–2 µm vertical; ±2 µm height accuracy; ±1% volume accuracy | Industry-typical values |
| 0.4 mm BGA paste target | 8,000–14,000 mil³ per pad; height tolerance ±15 µm; offset <50 µm | Industry-typical values |
| 2D / 3D AOI | Missing part, offset, polarity, bridging and insufficient solder; 3D adds fillet volume and coplanarity | Line capability |
| 3D AOI false calls | 50–70% fewer than 2D alone | Industry-typical value |
| 2D X-Ray | Transmission imaging of hidden joints on BGA, CSP and QFN | Line capability |
| Void criteria, IPC-7095 | Class 2 ≤25% individual, ≤40% total; Class 3 ≤10% individual, ≤25% total | Standard clause |
| ICT | Bed-of-nails in-circuit test, fixture design included | Line capability |
| ICT cycle | 5–30 seconds per board at about 2.54 mm probe pitch | Line capability |
| Flying probe | No fixture required; lower total cost below 500 boards a year | Line capability |
| Fixture break-even | Above 2,000 boards a year the bed-of-nails fixture wins | Line capability |
| FCT | Functional test bench with fixture and program development against your test plan | Line capability |
| JTAG boundary scan | IEEE 1149.1 chain test covering interconnects a probe cannot reach | Standard clause |
| Burn-in | Temperature-controlled burn-in room | Line capability |
| Hi-Pot | Dielectric withstand test for safety isolation | Line capability |
| FAI | First-article inspection report carrying SPI and AOI data with workmanship criteria | Line capability |
| Ionic contamination, ROSE | IPC-TM-650 Method 2.3.25: Class 2 ≤1.56, Class 3 ≤0.78 µg NaCl eq/cm² | Standard clause |
| Inspection configuration | Baseline chain: automatic paste printing, 3D SPI, placement, reflow, AOI. X-Ray is configured per project | Line capability |
HOW A TEST STRATEGY IS BUILT
Six steps from paste to paperwork
The order matters: you cannot inspect a void you have already covered, and you cannot functionally test a board whose nets you have not yet checked.
2D / 3D AOI after reflow
Presence, position, polarity, bridging and solder volume, at a false-call rate the 3D height data is there to reduce.
2D X-Ray on BGA / CSP / QFN
Added where the design hides its joints, and judged against the IPC-7095 void limits for the acceptance class on the drawing.
Electrical test
ICT on a bed-of-nails fixture where annual volume justifies it, flying probe where it does not.
Functional and environmental test
Powered functional test to your plan, JTAG boundary scan, burn-in and Hi-Pot where the product class calls for them.
Documentation
First-article inspection report, ROSE ionic contamination result where specified, and lot-level traceability filed against the build.
CAPABILITY LIST
Six test capabilities
CLOSED LOOP
3D SPI with feedback
Volume, height, area and offset measured automatically, with out-of-limit results correcting the printer rather than waiting for reflow to make the defect permanent. Industry data puts 60–70% of surface-mount defects in the printing step.
OPTICAL
2D and 3D AOI
Missing parts, offset, polarity, bridging and insufficient solder, with 3D height data adding fillet volume and coplanarity. Industry-typical false calls drop 50–70% against 2D alone.
THROUGH THE PACKAGE
2D X-Ray
Transmission imaging of BGA, CSP and QFN joints, assessed against the IPC-7095 void limits for your acceptance class. Configured per project, not switched on for every build.
ELECTRICAL
ICT on a bed-of-nails fixture
Fixture design and build included, at a cycle time of 5–30 seconds per board. The fixture NRE is quoted against your annual volume, because below about 500 boards a year it does not pay back.
POWERED
FCT and flying probe
Functional test bench with fixture and program development to your test plan, and flying probe for high-mix, low-volume work where a fixture would never amortise.
SCREENING
JTAG, burn-in, Hi-Pot and FAI
IEEE 1149.1 boundary-scan chain testing, temperature-controlled burn-in, dielectric withstand testing and a first-article report carrying SPI and AOI data.
FIXTURE ECONOMICS
What the test tooling costs, and when it pays back
Fixture NRE is a technical selection question before it is a price question: the answer depends on how many boards a year will cross the fixture.
General test fixture NREUSD 2,000–10,000+
ICT bed-of-nails fixture NREUSD 2,000–50,000+
Below about 500 boards a yearFlying probe wins — no fixture at all
Above about 2,000 boards a yearBed-of-nails wins — the 5–30 second cycle pays the fixture back
ICT cycle time5–30 seconds per board at about 2.54 mm probe pitch
FCT bench and programScoped against your test plan, quoted per project
Scheduling effect of fixture NREAdds 1–2 weeks before the test-ready date
How to read the row aboveA scheduling quantity, not a price; confirmed by the test engineer at quotation
TOOLING AND PROGRAMS
What the fixture money buys
FIXTURE
Bed-of-nails fixture and probes
Designed from your netlist and test-point list, with pogo-pin selection and the mechanical structure to hold the board flat across the probe field. NRE falls between USD 2,000 and USD 50,000+ depending on node count and mechanics.
BENCH
FCT bench and test program
Test bench, load and supply hardware and program development, executed against the test plan you supply. Where your plan does not exist yet, we scope one and quote it before programming starts.
NO FIXTURE
Flying-probe program and test points
Requires a test-point list from the design side, which is part of the DFM checklist. No fixture means no NRE, which is why it is the better total cost below 500 boards a year.
SCREENING
Burn-in boards and sockets
Burn-in boards, device sockets and temperature-controlled burn-in stations. Duration and profile are set by your specification: no industry-standard burn-in duration exists to quote against.
COMMERCIALS
Order size, lead time and test development charges
| Item | Value |
|---|---|
| Minimum order, chip passives 0603–2225, SOT, SOD, MELF | 50 pcs + 30 spares |
| Minimum order, all other packages | 100 pcs + 50 spares |
| Prototype quantities | Quoted per order |
| 1–10 pieces | 3–7 working days |
| 10–1,000 pieces | 5–10 working days |
| 5,000 pieces | About 3 weeks |
| Volume, after components are kitted | 3–4 weeks ex-works |
| Long-lead semiconductors | Can add 12–26 weeks |
| NRE | USD 0–150, waived on most projects |
| First-article inspection | USD 100–300 |
| IC programming | USD 50–200 |
| General test fixture NRE | USD 2,000–10,000+ |
| ICT bed-of-nails fixture NRE | USD 2,000–50,000+ |
| Fixture scheduling | Adds 1–2 weeks, a schedule figure and not a price |
| Unit premium, 5–20 pieces | +30–40% |
| Unit premium, 101–499 pieces | +5–15% |
Every date is an assembly lead time ex-components, counted from the point the last component is kitted. Accuracy of this page: quality and inspection system · SMT assembly · through-hole & DIP · mixed-technology · prototype to production · all capabilities
SECTOR REQUIREMENTS
What each sector usually adds to the test plan
Industrial automation
Wide-temperature function
Functional test across −40…+85 °C, with vibration and EMC consistency checks against the declared specification.
Medical devicesTraceability and validation
Lot-level traceability, IQ/OQ/PQ validation documentation and a functional test record retained per build.
Automotive & EVPPAP and heavy-copper joints
PPAP documentation, 8D reporting and X-Ray void assessment on the heavy-copper joints that carry the current.
Consumer & IoTFast functional coverage
Flying probe and functional test configured for short runs, plus support during the certification testing of the finished product.
Energy & powerDielectric and void control
Hi-Pot dielectric withstand testing plus void criteria on heavy-copper joints where thermal cycling is the life-limiting factor.
Telecom & data centreDense arrays and high-speed nets
High-density BGA void assessment and functional testing that exercises the high-speed interfaces on the board.
WHAT IS NOT INCLUDED
Four statements that keep this page honest
Inspection is configured per project
There is no blanket coverage claim here. Test items are selected for your board, priced individually and written into the quotation, so you can see exactly what will and will not be inspected.
X-Ray follows the design, not the product line
The baseline chain is automatic paste printing, 3D SPI, placement, reflow and AOI. X-Ray is added where the assembly hides its joints, and it is quoted as the line item it is.
Every criterion is named and checkable
IPC-7095 for voiding, IPC-A-610 Class 2 / Class 3 for workmanship, IPC J-STD-001 for the process, IPC-TM-650 Method 2.3.25 for ROSE and IEEE 1149.1 for boundary scan. All are public documents your auditor already holds.
System scope is stated, not implied
ISO 9001:2015, ISO 13485:2016 with the scope Production of PCBA, and IATF 16949:2016 with the product-design exclusion. ISO 13485 is a quality management system certificate: it is not an FDA approval and not an EU MDR certificate. Lot-level traceability is provided and buyer audit rights go into the quality agreement.
NEXT STEP
Send the drawing with its acceptance class
The class on the drawing sets the void limit, the workmanship criteria and whether X-Ray belongs in the flow. Send the class, your annual volume and the test plan you already have, and the reply will list each test item with its cost.
Reply within one business day
Useful with the enquiry: acceptance class, annual volume, existing test plan, test-point list and any net that must be functionally exercised.